FPGA journey

As mentioned in a previous post one of the things triggered by my descent into the nand2tetris hole was the decision start working with FPGAs. I will not explain what FPGAs are , there are plenty of resources online for that. THe one I started with was Nandland: FPGA, VHDL, Verilog Examples & Tutorials.

Instead I will describe my journey and some of the gotchas I fell into. Reminder : I want to build an implementation of the Hack system on an FPGA, with the ultimate goal of running a simple Unix version on it.

Starter system

I started with the go board from the nandland site: The Go Board – Introduction (nandland.com). This seemed like a good start, was cheap and had good features. I certainly liked the VGA connector. I also bought the book by the nandand site owner Getting Started With FPGAs – Book for Beginners in VHDL, Verilog, and FPGAs – Nandland. This is a good basic intro, it does not require you to have the go board but covers it if you do have it.

The FPGA in the go board is the Lattice ICE40 HX1K. This is a relatively lightweight FPGA, in particular it doesnt have a lot of block RAM (more later), but is enough to get going.

Toolchain

Next comes the choice of languages and tools. You have to decide Verilog or VHDL. They basically have the same features, I chose Verilog because I preferred the syntax. I also found that there more open source tools supporting it.

Next you need a toolset that takes verilog, ‘compiles’ it and then loads it onto the FPGA. Each chip vendor has their own. Lattice has 2

• IceCube
• Lattice Diamond

IceCube is a free tool for use with ICE40 devices, the other one is a paid tool for other devices. I started out using IceCube but decided that I wanted a simpler environment. ICE40 devices have been reverse engineered and there are now open source tools, GUI and command line that support them:

• yosys, a verilog compiler
• nextpnr, a place and route tool

I then found apio Welcome to apio’s documentation! — apio 0.4.0 documentation (apiodoc.readthedocs.io). This is a command line tool that manages all the other command line tools and makes ICE40 programming a breeze. So I settled on this dev environment:

• VSCode
• VSCode plugin Verilog-HDL/SystemVerilog/Bluespec SystemVerilog – Visual Studio Marketplace
• apio

It then became very simple: edit the verilog, run apio upload, done

Second FPGA

I got a simple Hack system working on the go board. But was aware of its limitations, not enough RAM (hack wants 128kb), only 2 8 seg displays, no I2c expansion. So I chose my next board, the Alachrity CU Alchitry Cu FPGA Development Board (Lattice iCE40 HX) – DEV-16526 – SparkFun Electronics and its snap in daughter board the Alachrity IO.

This uses the largest ICE40 device, has an I2C connector and the IO daughter baord has lots of lights, knobs and switches.

This is the system I first got really serious with a Hack emulator. Ironically the CPU itself was almost disappointingly trivial, maybe a few hours work. The real challenge was talking to the board to load code onto it. This I did via the emulated TTY port over USB.

Block RAM

Most FPGAs have RAM built into them, usually call Block RAM or Embedded RAM.You can add external RAM to an FPGA and many hobbyist boards do this, but they are more expensive and much harder to program.

The hack system needs 128kb of memory. 64k of instruction store, 64k of data store. You can obviously build a system with less but I wanted the full size.

Looking here you can see the amount of RAM inside each ICE40 FPGA. iCE40 LP/HX | Low Power, High Performance FPGA (latticesemi.com)

• 1k (go board) has 64kbits
• 8k (alachrity AU) has 128kbits

I misread this as kbytes :(. So still not big enough. So I upgraded again … next episode