FPGA journey part 2

In the previous post I talked about my experience with ICE40 based FPGA boards. In the end I abandoned them because they did not have enough block RAM (I need 128kb). After looking at the Alcrity Au Alchitry Au FPGA Development Board (Xilinx Artix 7) – DEV-16527 – SparkFun Electronics and Au+ I decided on a complete switch. So I selected the Basys3 Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users – Digilent. This is based around the Xlinix (AMD now) Altera 7 FPGA.

This has :-

• 256kb block RAM
• 4 pmod connectors for extra devices
• 4 8 seg displays plus a ton of leds and switches
• VGA connector
• USB HID connector.

Just what I need.

The sad part is thqat I have to abandon the toolchain of the ICE40 and use Xilinx own IDE : Xilinx Vivado Design Suite. This is a big piece of software. It has lots of scripting capabilities using TCL.

I landed on fusesoc olofk/fusesoc: Package manager and build abstraction tool for FPGA/ASIC development (github.com). This is like apio but for all FPGA vendors.

So thats where I am now